Method of manufacturing SRAM having enhanced cell ratio

ABSTRACT

An SRAM cell and a method of manufacturing the same are disclosed. An SRAM cell including pull down devices, access devices and pull up devices each having source and drain regions with LDD structure, the source and drain regions of the access devices having: N +  source and drain regions; N −  source and drain regions formed under the N +  source and drain regions; and P −  impurity regions whose predetermined portion is overlapped with the N −  source and drain region.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a divisional of U.S. Ser. No. 08/825,073filed Mar. 27, 1997 now U.S. Pat. No. 5,955,746 from which priority isclaimed under 35 U.S.C. §119 and 35 U.S.C. §120.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device andmethod of manufacturing the same, and more particularly, to a StaticRandom Access Memory cell capable of enhancing cell ratio and amanufacturing method thereof.

2. Description of the Related Art

A semiconductor memory device is classified into a dynamic random accessmemory (DRAM) and a static random access memory (SRAM) according to itsmethod of storing data. SPAM is particular significant due to its highspeed, low power consumption, and simple operation. In addition, unlikethe DRAM, the SRAM has advantage of an easy design as well as not havingto regularly refresh stored data.

In general, SRAM cell includes: two driving transistors which arepull-down devices; two access devices; and two pull-up devices. The SRAMcell is further classified as a full CMOS cell, a high roadresistor(HRL) cell, or a thin film transistor (TFT) cell according tothe type of the pull-up devices used.

The full CMOS cell utilizes a P-channel bulk MOSFET as the pull-updevice. The HRL cell utilizes a polysilicon having a high resistancevalue as the pull-up device, and TFT cell utilizes P-channel polysiliconTFT as the pull-up device. Of the above-mentioned structures, the SRAMcell with the full CMOS cell structure has optimal operational deviceproperties and can be fabricated with a simple process. It, however, hasboth NMOS and PMOS transistors in the unit cell, resulting in a largecell size. Therefore, it is applied to the memory device having a smallcapacitance. On the other hand, SRAM cells with the HRL cell and the TFTcell structures have relatively poor performance and is complicated intheir fabrication. Because of their smaller cell size, however they aregenerally applied to semiconductor memory device in cases of largercapacitance.

FIG. 1 is a conventional circuit diagram of an SRAM cell with the fullCMOS cell structure.

As shown in this diagram, sources S1 and S2 of PMOS transistors Q1 andQ2 for use in pull-up devices are connected to VDD. Drains D1 and D2 ofthe PMOS transistors Q1 and Q2 are respectively connected in series toeach drains D3 and D4 of NMOS transistors Q3 and Q4 for use in pull-downdevices at nodes N1 and N2. Sources S3 and S4 of the NMOS transistors Q3and Q4 are connected to VSS. Gates G1 and G2 of the PMOS transistors Q1and Q2 are respectively connected to gates G3 and G4 of the NMOStransistors Q3 and Q4, and these connection points thereof arerespectively cross-coupled with the nodes N1, N2. In NMOS transistors Q5and Q6 for use in access devices, gates G5 and G6 are connected to aword line W/L, sources S5 and S6 are respectively connected to bit linesB/L1 and B/L2. Drains D5 and DG of NMOS transistors Q5 and Q6 arerespectively connected to the drains D3 and D4 of the NMOS transistorsQ3 and Q4 at the nodes N1, N2.

In the above described SRAM cell, the NMOS transistors Q5 and Q6 areturned on by turning on the word line W/L, to store data in a HIGH statein the node N1 and data in a LOW state in the node N2. Data in a HIGHstate is inputted to the bit line B/L1 and data in a LOW state isinputted to the bit line B/L2, so that the PMOS transistor Q1 and NMOStransistor Q4 are turned on, and PMOS transistor Q2 and NMOS transistorQ3 are turned off. Therefore, the node N1 becomes a HIGH state and thenode N2 becomes a LOW state. Furthermore, although the word line W/L isturned off, the node N2 is latched to maintain a LOW state and the nodeNi is maintained at a HIGH state.. Accordingly, data is stored in thenodes N1 and N2 respectively.

Meanwhile, one of the factors determining the characteristics of theSRAM is the current driving capability ratio of the pull down device,otherwise known as the driving device and the access device(I_(DSAT DRIVER TRANSISTOR)/I_(DSAT ACCESS TRANSISTOR)), otherwise knownas cell ratio. A higher cell ratio results in improved performance ofthe SRAM. Therefore when the current amount of the pull down device islarge and the current amount access device is small, the performance ofthe SRAM cell is improved.

An operation of the SRAM related to the cell ratio is as follows. Incase the data in a low state is stored in the node N1 and the data in ahigh state is stored in the node N2, the voltage of the node N1 isdetermined by the current amount ratio of the NMOS transistors Q5 and Q6for use in access devices and the NMOS transistors Q3 and Q4 for use inpull down devices. Accordingly, the node N1 is intended to maintain thelow voltage with the increase of the current amount of the NMOStransistors Q3 and Q4, and with the decrease of that of the NMOStransistors Q5 and Q6. If so, the voltage of the node N1 is notdrastically changed from the low state when the NMOS transistors Q5 andQ6 are turned on during the reading operation, even though the voltageof the bit line B/L1 is changed. In case the voltage variation of thenode N1 is small, the voltage of the cross-coupled node N2 is stillmaintained in the high state.

Therefore, conventionally, the cell ratio is controlled in a mannerwherein width of the NMOS transistor for use in access device is reducedand its length is increased to thereby reduce its the current amount,and width of the NMOS transistor for use in pull-down device isincreased and its length is reduced to thereby increase its the currentamount. The width and length of the transistor, however, cannot bereduced below a predetermined level, and therefore there is arestriction in reducing the size of the cell to enhance the cell ratio.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide an SRAMcell and manufacturing method of the same, which selectively reduce theconcentration of impurity ion of source/drain regions of an accessdevices, and increases a parasitic resistance of the access devices,thereby reducing the current amount of access devices and enhancing thecell ratio of the SPAM cell.

In accordance with one embodiment, there is provided a SRAM cellincluding pull down devices, access devices and pull up devices eachhaving source and drain regions with LDD structure, the source and drainregions of the access device having; N⁺ source and drain regions; N⁻source and drain regions formed under the N⁺ source and drain regions;and a P⁻ impurity region wherein a predetermined portion thereof, isoverlapped with the N⁻ source and drain regions.

In this embodiment, the concentration of N type impurity of a regionwherein said P⁻ impurity region and said N⁻ source and drain regions ofsaid access devices are overlapped, is lower than that of said N⁻ sourceand drain regions.

There is also provided a method of manufacturing an SPAM celt havingpull down devices, access devices and pull up devices, the manufacturingmethod including the steps of: providing a semiconductor substrate ofwhich an active region is defined and a gate insulating layer and agates are formed on thereof; respectively forming N⁻ source and drainregions in the substrate of both sides of gates of the pull down devicesregion and the access devices region; and forming P⁻ impurity regions onpredetermined portions of the N⁻ source and drain regions of the accessdevices region.

In this embodiment, the impurity concentration of the P⁻ impurityregions is lower than that of the N⁻ source and drain regions.

BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS

The objects and feature of the invention may be better understood withreference to the following detailed description, appended claims, andattached drawings wherein:

FIG. 1 is an equivalent circuit diagram of a conventional SRAM cellhaving a full CMOS structure;

FIG. 2 is a plan view of an SRAM cell having a full CMOS structure inaccordance with a preferred embodiment of the present invention; and

FIGS. 3A and 3B are sectional views showing.a method for manufacturingthe SRAM cell in accordance with a preferred embodiment of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

A preferred embodiment according to the present invention is describedbelow with reference to the attached drawings.

Referring to FIG. 2 with cross reference to FIG. 1, A1 and A2 denote theactive regions of PMOS transistors Q1 and Q2 for use in pull up devices,B1 and B2 denote the active regions of NMOS transistors Q3 and Q4 foruse in pull down devices and NMOS transistors Q5 and Q6 for use inaccess devices. C1 to C6 denote contact regions. Here, contact regionsC1 and C2 denote node contact regions of node N1 and N2. The NMOStransistors Q3 and Q4 for use in pull down devices and the NMOStransistors Q5 and Q6 for use in access devices have in common the nodecontact regions C1 and C2 with in active regions B1 and B2 respectively.C3 and C4 denote contact regions of source S5 and S6 of the NMOStransistors Q5 and Q6. C5 denotes contact regions of source S1 and S2 ofPMOS transistor Q1 and Q2, and C6 denotes contact regions of source S3and S4 of the NMOS transistor Q3 and Q4. There are also provided wordlines 34 a, 34 b, 54 and mask pattern M used for forming P⁻ source/drainregions of the PMOS transistors Q1 and Q2 for use in pull up devices.Here, the mask pattern M is an open pattern to expose the active regionsA1 and A2 of the NMOS transistors Q3 and Q4 for use in pull downdevices, and also expose a predetermined portion of the active regionsB1 and B2 on both sides of the word line 54 of the NMOS transistors Q5and Q6 for use in access devices.

Meanwhile, FIG. 2 illustrates only the full CMOS SRAM cell structure,the above structure can be also applied to the HRL SEAM and P-channelpolysilicon TFT SRAM structures.

FIGS. 3A and 3B are the sectional views of an NMOS transistor Q3 for usein pull down device and the NMOS transistor Q5 for use in access deviceof SPAM cell taken along the line X-X′ of FIG. 2. With reference toFIGS. 3A and 3B, a manufacturing method of the above-mentioned SRAM cellwill be described below in detail.

As illustrated in FIG. 3A, isolating layers 2 are formed on apredetermined portion of a semiconductor substrate 1. Gate insulatinglayers 33 and 53, and gates 34 a and 54 are respectively formed on thesubstrate between the isolating insulating layers 2. Thereafter, an N⁻impurity ion, preferably P ion, is ion implanted into substrate 1 ofboth sides of the gates 34 a and 54 to a concentration of 2×10¹³ to5×10¹³ ions/cm². Therefore, N⁻ source regions 35 a and 55 a and commonN⁻ drain region 55 a/55 b of the NMCS transistor Q3 for use in pull downdevice and NMOS transistor Q5 for use in access device drain region 35 bof pull down transistor Q3 is formed in the substrate 1. P⁻ impurityion, preferably B or BF₂ ion is then ion implanted to a concentration of1×10¹³ to 3×10¹³ ions/cm² into a predetermined portion of the N⁻source/drain region 55 a and 55 b both sides of the gate 54 of the NMOStransistor Q5 for use in access device. Therefore, a predeterminedportion of the N⁻ source and drain regions 55 a and 55 b of the NMOStransistor Q5 for use in access device is overlapped wherein P⁻ ionimplanted regions 56 a and 56 b are formed. The P⁻ ion implanted regionsare formed on a predetermined portion of the N⁻ source and drain regionsof the access devices wherein a predetermined portion of the P⁻ impurityregion is overlapped with a side edge of the N⁻ source and drainregions, the side edge located adjoining the gate insulating layer ofthe access device, the P⁻ impurity region extending from the gateinsulating layer entirely around the side edge of the N⁻ source anddrain regions and terminating below the N⁻ source and drain regions toform the overlap of the P⁻ impurity region by the Nsource and drainregion.

Here, even though a process for forming P⁻ source and drain regions ofthe PMOS transistors Q1 and Q2 for use in pull up devices is notillustrated, the P⁻ ion implanted regions 56 a and 56 b are formed withthe P⁻ source and drain regions during the above process for forming P⁻source and drain regions by the ion implanting process using the maskpattern M(refer to FIG. 2). The concentration of B ion, which is the P⁻type impurity ion of the P⁻ ion implanted regions 56 a and 56 b, shouldbe lower than that of P⁻ ion, which is the N type impurity ion of the N⁻source and drain regions 35 b/55 b and 55 a. Accordingly, theconcentration of the N type impurity of the access transistor Q5 becomeslower than that of the N type impurity of other NMOS transistor Q3. Thatis, the concentration of P ion, which is the N type impurity ion of theN⁻ source and drain regions 55 a and 55 b of the NMOS transistor Q5 foruse in access device, is about 2×10¹⁸ to 5×10¹⁸ ions/cm³. Theconcentration of B ion, which is the P type impurity ion of the P⁻ ionimplanted regions 56 a and 56 b, is about 1×10¹⁸ to 3×10¹⁸ ions/cm³.Accordingly the concentration of the N type impurity of regions whereinthe N⁻ source and drain regions 55 a and 55, and the P ion implantedregions 56 a and 56 b are overlapped, is about 1×10¹⁸ to 2×10¹⁸ions/cm³.

As illustrated in FIG. 3B, the insulating layer, preferably, an oxidelayer or nitride layer is deposited on the structure of FIG. 3A. Surfaceof the gates 34 a and 54 are then etched by the anisotropic blanketetching, so that LDD spacers 37 and 57 of the insulating layer areformed on both side walls of the gates 34 a and 54. Thereafter N⁺impurity ion, preferably, As ion is ion implanted to a concentration of1×10¹⁵ to 7×10¹⁵ions/cm² into the substrate 1 of both sides of spacers37 and 57, so that the source and drain regions 38 a, 38 b/58 b and 58 aof the NMOS transistor Q3 for use in pull down device and the NMOStransistors Q5 for use in access device are formed respectively. Here,the concentration of As, which is the N type impurity ion of the N⁺source and drain regions 38 a, 38 b/58 b and 58 a, is about 3×10¹⁹ to3×10²⁰ ions/cm³.

An intermediate insulating layer 9 is then formed on the overall surfaceof the substrate, and etched to expose the contact portion of the N+source and drain regions 38 a, 38 b/58 b and 58 a, thereby formingcontact holes. A metal layer is then deposited on the intermediateinsulating layer 9 to fill the contact holes. The metal layer is thenpatterned thereby forming metal interconnection layers 10 a, 10 b and 10c.

According to the present invention, a predetermined portion of the N⁻source and drain regions is overlapped with the P⁻ ion implanted regionin the access devices of SRAM cell, so that the concentration of theimpurity ion of the N⁻ source and drain regions is selectively low,thereby increasing the parasitic resistance of access devices.Accordingly, the current amount of the access devices is also decreased,thereby enhancing the cell ratio of the SRAM cell.

Furthermore, the invention can implement higher integration of device byreducing the size of the cell.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications of the illustrative embodiments,as well as other embodiments of the invention, will be apparent topersons skilled in the art upon reference to this description. It istherefore contemplated that the appended claims will cover any suchmodifications or embodiments as falling within the true scope of theinvention.

What is claimed is:
 1. A method for manufacturing an SRAM cell havingpull down devices, access devices and pull up devices comprising thesteps of: providing a semiconductor substrate having an active regiondefined by an isolating layer, a gate insulating layer and gates formedthereon; respectively forming N⁻ source device regions and drain deviceregions for pull down device regions and access device regions on thesubstrate on both sides of the gates of the pull down devices and theaccess devices; and forming P⁻ impurity regions within the semiconductorsubstrate on both sides of the gates of the access device regionsincluding a predetermined portion of the N⁻ source device regions anddrain device regions of the access device regions wherein the P⁻impurity regions overlap with the predetermined portion of the N⁻ sourcedevice regions and drain device regions of the access device regions. 2.The method as claimed in claim 1, wherein the N⁻ source and drainregions of the pull-up devices in the SRAM cell are formedsimultaneously with the forming of the P⁻ impurity regions of thepull-up devices.
 3. The method as claimed in claim 2, wherein theimpurity concentration of the P⁻ impurity regions is lower than that ofN⁻ source and drain regions.
 4. The method as claimed in claim 3,wherein a concentration of ions of the N⁻ source and drain regions is2×10¹⁸ to 5×10¹⁸ ions/cm³.
 5. The method as claimed in claim 3, whereina concentration of BF2 ions of P⁻ impurity regions is 1×10¹⁸ to 3×10¹⁸ions/cm³.
 6. The method as claimed in claim 3, wherein a concentrationof the N type impurity in regions wherein the N⁻ source and drainregions and the P⁻ ion implanted regions and are overlapped is 1×10¹⁸ to2×10¹⁸ ions/cm³.
 7. The method as claimed in claim 1, further comprisingthe steps of: forming insulating layer spacers on side walls of thegates; and forming N⁺ source and drain regions in the substrate on sidesof the spacers of the pull down device regions and the access deviceregions.
 8. The method as claimed in claim 7, wherein a concentration ofAs ions of the N⁺ source and drain regions is 3×10¹⁹ to 3×10²⁰ ions/cm³.9. The method as claimed in claim 1, wherein the pull up devices are Pchannel bulk MOSFETs.
 10. The method as claimed in claim 1, wherein thepull up devices are resistors.
 11. The method as claimed in claim 1,wherein the pull up devices are P channel polysilicon TFTs.
 12. Themethod of claim 1, wherein said step of forming is carried outexclusively for forming the access device regions.
 13. the method ofclaim 1, wherein said SRAM cell has a characteristic cell ratio which isimproved by said forming step reducing current in the access deviceregions in relation to current in the pull-down device regions.
 14. Themethod as claimed in claim 7, wherein a concentration of the N typeimpurity of regions wherein the N⁻ source and drain regions, and the P⁻ion implanted regions and are overlapped is 1×10¹⁸ to 2×10¹⁸ ions/cm³.15. A method for manufacturing an SRAM cell having pull down devices,access devices and pull up devices comprising the steps of: providing asemiconductor substrate having an active region defined by an isolatinglayer, and a gate insulating layer and a gates formed on thesemiconductor substrate; forming an insulating layer spacers on bothside walls of the gates; respectively forming N⁻ source and drainregions on the semiconductor substrate of both sides of gates of thepull down devices region and the access devices region, wherein theconcentration of the N⁻ source and drain regions is 2×10¹⁸ to 5×10¹⁸ions/cm³; forming P⁻ impurity regions within the semiconductor substrateof both sides of the gate including a predetermined portion of the N⁻source and drain regions of the access device, wherein the concentrationof P⁻ impurity regions is 1×10¹⁸ to 3×10¹⁸ ions/cm³, wherein the Pimpurity regions is overlapped with the predetermined portion of the N⁻source and drain regions of the access device; and forming N⁺ source anddrain regions in the substrate of both sides of said spacers of saidpull down devices region and said access devices region.
 16. The methodof claim 15, wherein said step of forming is carried out exclusively forforming the access device regions.
 17. The method of claim 15, whereinsaid SRAM cell has a characteristic cell ratio which is improved by saidforming step reducing current in the access device regions in relationto current in the pull-down device regions.
 18. Method for forming anSRAM cell having a cell ratio defined by a ratio between a drivingdevice current and an access device current, comprising the steps of:forming the SRAM cell with driving devices, access devices and pull-updevices each having source and drain regions with a lightly doped drainstructure; and forming the source and drain regions of the accessdevices by forming first (N⁺) source and drain regions, second (N⁻)source and drain regions formed under the first source and drainregions, and impurity regions (P⁻) with a predetermined portion thereofoverlapping the second source and drain regions such that the cell ratiois increased by reducing the access device current in relation to thedriving device current.
 19. The method of claim 18, wherein the impurityregions have an impurity concentration lower than a concentration ofions in the source and drain regions.
 20. The method of claim 18,wherein the reducing of the access device current is accompanied byincreased parasitic resistance of the access devices.